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| 133mhz spread spectrum ftg for mobile pentium? iii platforms W254B rev 1.0, november 20, 2006 page 1 of 16 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax:(408) 855-0550 www.spectralinear.com w 254b features ? maximized emi suppression using cypress?s spread spectrum technology (?0.5% and 0.5%) single chip system ftg for mobile intel ? platforms two cpu outputs seven copies of pci clo ck (one free running) seven sdram clock (one dclk for memory hub) two copies of 48 mhz cloc k (non-spread spectrum) optimized for usb reference input and video dot clock three 3v66 hublink/agp outputs one vch clock (48 mhz non-ssc or 66.67 mhz ssc) one apic outputs one buffered reference output supports frequencies up to 133 mhz smbus interface for programming power management control inputs key specifications cpu, sdram outputs cycle-to-cycle jitter: .............. 250 ps apic, 48 mhz, 3v66, pci outputs cycle-to-cycle jitter: ................................................... 500 ps cpu output skew: ...................................................... 150 ps 3v66 output skew: ..................................................... 175 ps apic, sdram output skew: ...................................... 250 ps pci output skew:........................................................ 500 ps vddq3 (ref, pci, 3v66, 48 mhz, sdram): ......... 3.3v5% vddq2 (cpu, apic):........2.5v5%in selectable frequency table 1. pin selectable frequency input address output frequencies fs1 fs0 cpu sdram 48mhz pci apic ref 3v66 0 0 66 100 48 mhz 33 mhz 14.318 mhz 66 mhz 0 1 100 100 1 0 133 133 1 1 133 100 block diagram pin configuration vdd_48 vdd_ref x1 x2 gnd_ref gnd_pci pci_f/fs0^ pci1/fs1^ pci2 pci3 pci4 pci5 pci6 vdd_3v66 3v66_0 3v66_1 3v66_agp gnd_3v66 vch_clk gnd_48 usb dot gnd_core W254B ref apic vdd_apic cpu cpu_f gnd_cpu gnd_sdram sdram0 sdram1 sdram2 sdram3 gnd_sdram sdram4 sdram5 dclk vdd_sdram cpu_stp# pci_stp# pwr_dwn# sclk sdata vdd_core 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vdd_cpu vdd_sdram vdd_ref vdd_apic apic cpu cpu_f pci_f/fs0 xtal pll ref freq x2 x1 ref vdd_pci usb (48mhz) vch_clk osc vdd_cpu sclk pci1/fs1 stop clock control stop clock control pll 1 smbus logic dot (48mhz) pll2 pwr_dwn# vdd_48 sdata vdd_sdram sdram0:5 vdd_3v66 3v66_0:1 3v66_agp divider network pci2:6 dclk cpu_stp# pci_stp# 3v66_1 pci6 vdd_pci note: 1. internal pull-down or pull-up resistors present on inputs marked with * or ^ respectively. design should not rely solely on internal pull-up or pull-down resistor to set i/o pins high or low respectively.
W254B rev 1.0, november 20, 2006 page 2 of 16 pin definitions pin name pin no. pin type pin description cpu cpu_f 44, 43 o cpu clock outputs: frequency is set by the fs0:1 inputs or through serial input interface. the cpu output is gated by the clk_stop# input. pci1:6, pci_f/fs0, pci1/fs1 8, 10, 11, 12, 13, 6, 7 i/o 33-mhz pci outputs: except for the pci_f output, these outputs are gated by the pci_stop# input. upon power up, fs0 and fs1 is configured momentarily as input latches allowing various output frequencies to be selected. see table 2 . apic 47 o apic output: 2.5v fixed 33.3-mhz clock. this output is synchronous to the cpu clock. sdram0:5, dclk 40, 39, 37, 36, 34, 33, 32 o sdram output clocks: 3.3v outputs running at either 100 mhz or 133 mhz depending on the setting of fs0:1 inputs. dclk is a free-running clock. 3v66_0:1, 3v66_agp 15, 16, 17 o 66-mhz clock outputs: 3.3v fixed 66-mhz clock. usb 21 o usb clock output: 3.3v fixed 48-mhz, non-spread spectrum usb clock output. dot 22 o dot clock output: 3.3v fixed 48-mhz, non-spread spectrum signal. ref 48 o reference clock: 3.3v 14.318-mhz clock output. vch_clk 19 o video control hub clock output: 3.3v selectable 48-mhz non-spread spectrum or 66.67-mhz spread spectrum clock output. pwr_dwn# 28 i power-down control: 3.3v lvttl-compatible input that places the device in power-down mode when held low. cpu_stp# 30 i cpu output control: 3.3v lvttl-compatible input that stops only the cpu0 clock. output remains in the low state. pci_stp# 29 i pci output control: 3.3v lvttl-compatible input that stops pci1:6 clocks. output remains in the low state. sclk 27 i smbus clock input: clock pin for smbus circuitry. sdata 26 i/o smbus data input: data pin for smbus circuitry. x1 2 i crystal connection or external reference freq uency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal connection or as an external reference frequency input. x2 3 o crystal connection: connection for an external 14.318-mhz crystal. if using an external reference, this pin must be left unconnected. vdd_ref, vdd_pci, vdd _3v66, vdd_48, vdd_core, vdd_sdram, vdd_sdram 1, 9, 14, 23, 25, 31, 38 p 3.3v power connection: power supply for core logic, pll circuitry, sdram outputs buffers, pci output buffers, reference output buffers and 48-mhz output buffers. connect to 3.3v. vdd_apic, vdd_cpu 45, 46 p 2.5v power connection: power for apic and cpu output buffers. connect to 2.5v. gnd_ref, gnd_pci, gnd_3v66, gnd_48, gnd_core gnd_sdram, gnd_sdram, gnd_cpu 4, 5, 18, 20, 24, 35, 41, 42 g ground connection: connect all ground pins to the common system ground plane. W254B rev 1.0, november 20, 2006 page 3 of 16 overview the W254B is a highly integrated frequency timing generator, supplying all the required clock sources for an intel? archi- tecture platform using graphics-integrated core logic. functional description i/o pin operation pins 6 and 7 are dual-purpose l/o pins. upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. a short time af ter power-up, the logic state of each pin is latched and the pins then become clock outputs. this feature reduces device pin count by combining clock outputs with input select pins. an external 10-k : ?strapping? resistor is connected between each l/o pin and ground or vddq3. connection to ground sets a latch to ?0?, connection to vddq3 sets a latch to ?1?. figure 1 shows one suggested method for strapping resistor connection. upon W254B power-up, the first 2 ms of operation is used for input logic selection. during this period, the pci_f and pci1 clock output buffers are three-stated, allowing the output strapping resistor on each l/o pin to pull the pin and its associated capacitive clock load to either a logic high or logic low state. at the end of the 2-ms period, the established logic 0 or 1 condition of each l/o is pin is latched. next the output buffers are enabled, converting all l/o pins into operating clock outputs. the 2-ms timer starts when vddq3 reaches 2.0v. the input bits can only be reset by turning vddq3 off and then back on again. it should be noted that the strapping resistors have no signif- icant effect on clock output signal integrity. the drive impedance of the clock output is 40 : (nominal), which is minimally affected by the 10-k : strap to ground or vddq3. as with the series termination resistor, the output strapping resistor should be placed as close to the l/o pin as possible in order to keep the interconnecting trace short. the trace from the resistor to ground or vddq3 should be kept less than two inches in length to prevent system noise coupling during input logic sampling. when the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered, assuming that vddq3 has stabilized. if vddq3 has not yet reached full value, output frequency initially may be below target but will increase to target once vddq3 voltage has stabilized. in either case, a short output clock cycle may be produced from the cpu clock outputs when the outputs are enabled. cpu/ sdram frequency selection cpu output frequency is se lected with i/o pins 6 and 7. for cpu/sdram frequency programming information refer to table 2 . alternatively, freq uency selections are available through the serial data interface. notes: 2. range of reference frequency allowed is min. = 14.316 mhz, nominal = 14.31818 mhz, max. = 14.32 mhz. 3. frequency accuracy of 48 mhz must be +167 ppm to match usb default. power-on reset timer output three-state data latch hold qd W254B v dd clock load 10 k : output buffer (load option 1) 10 k : (load option 0) output low output strapping resistor series termination resistor figure 1. input logic selection through resistor load option table 2. frequency select truth table [2] input address output frequencies fs1 fs0 cpu sdram 48 mhz [3] pci apic ref 3v66 0 0 66 100 48 mhz 33 mhz 14.318 mhz 66 mhz 0 1 100 100 1 0 133 133 1 1 133 100 W254B rev 1.0, november 20, 2006 page 4 of 16 offsets among clock signal groups figure 2 and figure 3 represent the phase relationship among the different groups of clock outputs from W254B when it is providing a 66-mhz cpu clock and a 100-mhz cpu clock, respectively. it should be noted that when cpu clock is operating at 100 mhz, cpu clock output is 180 degrees out of phase with sdram clock outputs. table 3. 66 mhz group timing relationships and tolerances table 4. cpu to sdram cpu to 3v66 sdram to 3v66 3v66 to pci pci to apic usb & dot offset ?2.5 ns 7.5 ns 0.0 ns 1.5-3.5 ns 0.0 ns async tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns n/a figure 2. group offset waveforms (66 mhz cpu/100 mhz sdram clock) 0 ns 40 ns 30 ns 20 ns 10 ns cpu 66-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic33-mhz 0 ns 40 ns 30 ns 20 ns 10 ns cpu 100-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic33-mhz figure 3. group offset waveforms (100 mhz cpu/100 mhz sdram clock) W254B rev 1.0, november 20, 2006 page 5 of 16 table 5. 100 mhz group timing relationships and tolerances table 6. cpu to sdram cpu to 3v66 sdram to 3v66 3v66 to pci pci to apic usb & dot offset 5.0 ns 5.0ns 0.0 ns 1.5-3.5 ns 0.0 ns async tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns n/a figure 4. group offset waveforms (133-mhz cpu/100-mhz sdram clock) 0 ns 40 ns 30 ns 20 ns 10 ns cpu 133-mhz sdram 100-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic33-mhz table 7. 133 mhz/sdram 100 mhz group timing relationships and tolerances cpu to sdram cpu to 3v66 sdram to 3v66 3v66 to pci pci to apic usb & dot offset 0.0 ns 0.0 ns 0.0 ns 1.5-3.5 ns 0.0 ns async tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns n/a W254B rev 1.0, november 20, 2006 page 6 of 16 power-down control W254B provides one pwr_dwn# signal to place the device in low-power mode. in low-power mode, the plls are turned off and all clock outputs are driven low. figure 5. group offset waveforms (133-mhz cpu/133-mhz sdram clock) 0 ns 40 ns 30 ns 20 ns 10 ns cpu 133-mhz sdram 133-mhz 3v66 66-mhz pci 33-mhz ref 14.318-mhz usb 48-mhz dot 48-mhz cycle repeats apic33-mhz table 8. 133 mhz/sdram test mode group timing relationships and tolerance cpu to sdram cpu to 3v66 sdram to 3v66 3v66 to pci pci to apic usb& dot offset 3.75 ns 0.0 ns 3.75 ns 1.5-3.5 ns 0.0 ns async tolerance 500 ps 500 ps 500 ps 500 ps 1.0 ns n/a 1 2 center 0 ns 25 ns 50 ns 75 ns vco internal cpu 100-mhz 3v66 66-mhz pci 33 mhz apic 33-mhz pwrdwn sdram 100-mhz ref 14.318-mhz usb 48-mhz figure 6. W254B pwr_dwn# timing diagram [4, 5, 6, 7] W254B rev 1.0, november 20, 2006 page 7 of 16 notes: 4. once the pwr_dwn# signal is sampled low for two consecutive rising edges of cpu, clocks of interest will be held low on the n ext high-to-low transition. 5. pwr_dwn# is an asynchronous input and metastable conditions could exist. this signal is synchronized inside W254B. 6. the shaded sections on the sdram, ref, and usb clocks indicate ?don?t care? states. 7. diagrams shown with respect to 100 mhz. similar operation when cpu is 66 mhz. table 9. W254B maximum allowed current W254B condition max. 2.5v supply consumption max. discrete cap loads, v ddq2 = 2.625v all static inputs = v ddq3 or v ss max. 3.3v supply consumption max. discrete cap loads v ddq3 = 3.465v all static inputs = v ddq3 or v ss powerdown mode (pwr_dwn# = 0) < 1 ma < 1 ma full active 66 mhz fs1:0 = 00 (pwr_dwn# =1) 70 ma 280 ma full active 100 mhz fs1:0 = 01 (pwr_dwn# =1) 100 ma 280 ma full active 133 mhz fs1:0 = 11 (pwr_dwn# =1) 100 ma 280 ma W254B rev 1.0, november 20, 2006 page 8 of 16 spread spectrum frequency timing generation the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the ampli- tudes of the radiated electromagnetic emissions are reduced. this effect is depicted in figure 7 . as shown in figure 7 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is: db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 8 . this waveform, as discussed in ?spread spectrum clock generation for the reduction of radiated emissions? by bush, fessler, and hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is + 0.5% or ?0.5% of the selected frequency. figure 8 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. spread spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the smbus data stream. refer to page 10 for more details. ssftg typical clock frequency span (mhz) amplitude (db) spread spectrum enabled emi reduction spread spectrum non- frequency span (mhz) amplitude (db) center spread figure 7. clock harmonic with and without sscg modulation frequency domain representation max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 8. typical modulation profile W254B rev 1.0, november 20, 2006 page 9 of 16 serial data interface the W254B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. data protocol the clock driver serial protocol accepts only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transf erred. indexed bytes are not allowed. a block write begins with a slave address and a write condition. after the command code the core logic issues a byte count which describes how many more bytes will follow in the message. if the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. the byte count may not be 0. a block write command is allowed to transfer a maximum of 32 da ta bytes. the slave receiver address for W254B is 11010010. figure 9 shows an example of a block write. the command code and the byte count bytes are required as the first two bytes of any transfer. W254B expects a command code of 0000 0000. the byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. table 10 shows an example of a possible byte count value. a transfer is considered valid after the acknowledge bit corre- sponding to the byte count is read by the controller. the command code and byte count bytes are ignored by the W254B. however, these bytes must be included in the data write sequence to maintain proper byte allocation. W254B serial configuration map 1. the serial bits will be read by the clock driver in the following order: byte 0 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte 1 - bits 7, 6, 5, 4, 3, 2, 1, 0 byte n - bits 7, 6, 5, 4, 3, 2, 1, 0 2. all unused register bits (reserved and n/a) should be written to a ?0? level. all register bits labeled ?initialize to 0" must be written to zero during initialization. failure to do so may result in higher than normal operating current. note: 8. the acknowledgment bit is returned by the slave/receiver (W254B). 1 bit 7 bits 1 1 8 bits 1 start bit slave address r/w ack command code ack byte count = n ack data byte 1 ack data byte 2 ack ... data byte n ack stop 1 bit 8 bits 1 8 bits 1 8 bits 1 1 figure 9. an example of a block write [8] table 10.example of possib le byte count value byte count byte notes msb lsb 0000 0000 not allowed. must have at least one byte 0000 0001 data for functional and frequency select register (currently byte 0 in spec) 0000 0010 writes first two bytes of data (byte 0 then byte 1) 0000 0011 writes first three bytes (byte 0, 1, 2 in order) 0000 0100 writes first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 writes first five bytes (byte 0, 1, 2, 3, 4 in order) 0000 0110 writes first six bytes (byte 0, 1, 2, 3, 4, 5 in order) 0000 0111 writes first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 max. byte count supported = 32 W254B rev 1.0, november 20, 2006 page 10 of 16 note: 9. inactive means outputs are held low and are disabled from switching. these outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. byte 0: control register (1 = enable, 0 = disable) [9] bit pin# name pin description bit 7 19 vch_clk (active/inactive) bit 6 -- reserved drive to ?0? (active/inactive) bit 5 43 cpu_f (disabled/enabled) bit 4 44 cpu (disabled/enabled) bit 3 -- spread spectrum (1 = on; 0 = off) (active/inactive) bit 2 22 dot (48 mhz) (disabled/enabled) bit 1 21 usb (48 mhz) (disabled/enabled) bit 0 -- reserved drive to ?0? (active/inactive) byte 1: control register (1 = enable, 0 = disable) [9] bit pin# name pin description bit 7 -- reserved drive to ?0? (active/inactive) bit 6 -- reserved drive to ?0? (active/inactive) bit 5 33 sdram5 (disabled/enabled) bit 4 34 sdram4 (disabled/enabled) bit 3 36 sdram3 (disabled/enabled) bit 2 37 sdram2 (disabled/enabled) bit 1 39 sdram1 (disabled/enabled) bit 0 40 sdram0 (disabled/enabled) byte 2: control register (1 = enable, 0 = disable) [9] bit pin# name pin description bit 7 17 3v66_agp (disabled/enabled) bit 6 16 3v66_1 (disabled/enabled) bit 5 15 3v66_0 (disabled/enabled) bit 4 -- reserved drive to ?0? (active/inactive) bit 3 -- reserved drive to ?0? (active/inactive) bit 2 -- reserved drive to ?0? (active/inactive) bit 1 -- reserved drive to ?0? (active/inactive) bit 0 -- reserved drive to ?0? (active/inactive) byte 3: control register (1 = enable, 0 = disable) bit pin# name pin description bit 7 - reserved drive to ?0? (active/inactive) bit 6 13 pci6 (disabled/enabled) bit 5 12 pci5 (disabled/enabled) bit 4 11 pci4 (disabled/enabled) bit 3 10 pci3 (disabled/enabled) bit 2 8 pci2 (disabled/enabled) bit 1 7 pci1/fs1 (disabled/enabled) bit 0 -- sdram 133-mhz mode enable default is disabled = ?0?, enabled = ?1? W254B rev 1.0, november 20, 2006 page 11 of 16 byte 5 has been provided as an optional register to enable a greater degree of spread spectrum and overclocking perfor- mance for all pll1 outputs. (cpu, sdram, dclk, apic, pci, 3v66 and vch_clk) by enabling byte 5, (bits 5 and 6) spread spectrum can be increased to + 0.5% and /or overclocking of either 5%, 10% or 15% can be enabled. it is not necessary to access byte 5 if these additional features are not implemented. all outputs will default to 0% overclocking upon power up, with either 0% or ?0.5% spread spectrum. (spread spectrum on/off remains under byte 0, bit 3 control). note that 10% and 15% overclocking can only be enabled with spread spectrum turned off. note: 10. overclocking not tested; characterized at room temperature only. base frequency determined through hardware select pins, fs0 & fs1. byte 4: control register (1 = enable, 0 = disable) bit pin# name pin description bit 7 19 vch_clk ssc mode 0 = 48 mhz non-ssc (default) 1 = 66 mhz ssc (disabled/enabled) bit 6 - reserved drive to ?0? (active/inactive) bit 5 - reserved drive to ?0? (active/inactive) bit 4 - reserved drive to ?0? (active/inactive) bit 3 - reserved drive to ?0? (active/inactive) bit 2 - reserved drive to ?0? (active/inactive) bit 1 reserved drive to ?0? (active/inactive) bit 0 - reserved drive to ?0? (active/inactive) byte 5: control register (1 = enable, 0 = disable) bit pin# name pin description bit 7 - reserved drive to ?0? (active/inactive) bit 6 - spread spectrum and overclocking mode select. see table 11 (active/inactive) bit 5 - (active/inactive) bit 4 - reserved drive to ?0? (active/inactive) bit 3 - reserved drive to ?0? (active/inactive) bit 2 - reserved drive to ?0? (active/inactive) bit 1 reserved drive to ?0? (active/inactive) bit 0 - reserved drive to ?0? (active/inactive) table 11.spread spectrum and overclocking mode select byte 0 byte 5 ss % overclock % descr iption and comments bit 3 bit 5 bit 6 spread spectrum on 0 0 ?0.5% 0% no overclocking (default) 0 1 0.5% 0% no overclocking 1 0 ?0.5% 5% [10] 110.5% 5% [10] spread spectrum off 0 0 - 0% no overclocking 01 - 10% [10] 10 - 5% [10] 11 - 15% [10] W254B rev 1.0, november 20, 2006 page 12 of 16 dc electrical characteristics [11] note: 11. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 12. input leakage current does not include inputs with pull-up or pull-down resistors. absolute maximum dc power supply parameter description min. max. unit v dd3 3.3v core supply voltage ?0.5 4.6 v v ddq2 2.5v i/o supply voltage ?0.5 3.6 v v ddq3 3.3v supply voltage ?0.5 4.6 v t s storage temperature ?65 150 c absolute maximum dc i/o parameter description min. max. unit v ih3 3.3v input high voltage ?0.5 4.6 v v il3 3.3v input low voltage ?0.5 v esd prot. input esd protection 2000 v dc operating requirements parameter description condition min. max. unit v dd3 3.3v core supply voltage 3.3v5% 3.135 3.465 v v ddq3 3.3v i/o supply voltage 3.3v5% 3.135 3.465 v v ddq2 2.5v i/o supply voltage 2.5v5% 2.375 2.625 v v dd3 = 3.3v5% v ih3 3.3v input high voltage v dd3 2.0 v dd + 0.3 v v il3 3.3v input low voltage v ss ? 0.3 0.8 v i il input leakage current [12] 0 W254B rev 1.0, november 20, 2006 page 14 of 16 group skew and jitter limits output group pin-pin skew max. cycle-cycle jitter duty cycle nom vdd skew, jitter measure point cpu 150 ps 250 ps 45/55 2.5v 1.25v sdram 250 ps 250 ps 45/55 3.3v 1.5v apic 250 ps 500 ps 45/55 2.5v 1.25v 48mhz n/a 500 ps 45/55 3.3v 1.5v 3v66 175 ps 500 ps 45/55 3.3v 1.5v pci 500 ps 500 ps 45/55 3.3v 1.5v ref n/a 1000 ps 45/55 3.3v 1.5v vch_clk n/a 250 ps 45/55 3.3v 1.5v clock output wave 2.5v clocking 3.3v clocking test point test load t period duty cycle t high 2.0 1.25 0.4 t low t rise t fall t low t rise t fall t period duty cycle t high 2.4 1.5 0.4 output buffer interface interface figure 10. output buffer W254B rev 1.0, november 20, 2006 page 15 of 16 layout diagram 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 6 7 13 19 20 24 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors +2.5v supply 1 2 3 4 5 8 9 11 12 14 15 16 17 22 23 21 32 31 18 33 10 28 27 26 25 29 30 g v fb +3.3v supply c4 c1, c3 & c5 = 10?22 p f c2 & c4 = 0.005 p f 10 p f fb c1 c2 0.005 p f fb = dale ilb1206 - 300 (300 : @ 100 mhz) 10 p f 0.005 p f g g g g vddq2 vddq3 c3 c6 = 0.1 p f g g 10 : vddq3 c5 c6 g v g v g v g g g g v g v g v g v core W254B g g g g g g g g g g g g g g ceramic caps rev 1.0, november 20, 2006 page 16 of 16 W254B while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear inc., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. ordering information ordering code package name package type W254B x 48-pin tssop (6.1 mm) 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48 |
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